The present invention relates to the field of manufacturing semiconductor integrated circuit (IC) devices, and more particularly, to a method of fabricating metal gate complementary metal oxide semiconductor (CMOS) transistors with self-aligned source and drain regions.
In the present state of art, methods for manufacturing CMOS transistors in an integrated circuit which has a polysilicon gate electrode layer usually include a self-alignment technique to form the source and drain electrodes. As such, difficulties due to misalignment are reduced. Unfortunately, prior art self-alignment techniques cannot be utilized to produce a metal gate CMOS transistor. As a result, the channel length of the metal gate CMOS transistor cannot be as precisely defined as is desired. The resulting misalignment results in a larger leakage of current, and the metal gate cannot precisely cover the source region and the drain regions, and therefore the performance of the CMOS is reduced.